1. Field of the Invention
The present invention is related to electrostatic discharge (ESD) protection and, more particularly, to ESD protection systems in relatively low supply voltage integrated circuits (ICs).
2. Related Art
ESD protection circuits implemented at integrated circuit (IC) input/output (I/O) pads protect the ICs from unwanted ESD events, usually up to 2 kV. Typical ESD protection circuits are designed to turn off during normal operations and turn on during ESD events, and are coupled between the chip supply voltage line and ground in order to provide an adequate discharge path.
As ICs are fabricated into the sub-micron range, supply voltages are scaled down accordingly. For example, a 0.18 μm process requires a supply voltage of approximately 1.8 V, but a 0.13 μm process requires a reduced supply voltage of only 1.2 V. In low supply voltage ICs, the signal swing at the I/O pads should be as large as possible in order to maintain a sufficient signal-to-noise ratio (SNR).
A problem with ESD protection circuits in low supply voltage ICs is limited headroom at the I/O pads. Because the diodes in the ESD protection circuit must remain off during normal operations in order to prevent clipping the signal, the allowable signal swing at the I/O pads is limited. For example, a typical ESD protection circuit includes a first diode coupled between the supply voltage (VDD) and the I/O pad, and a second diode coupled between the I/O pad and ground. Typical diodes have a forward turn-on voltage of about 0.7 V. Therefore, the diodes will remain off as long as the signal swing at the I/O pad is above VDD by approximately 0.7 V and below ground by about 0.7 V. The ESD protection circuit restrains the signal swing at the I/O pad to less than VDD+1.4 V. If the signal swing at the I/O pad exceeds VDD+1.4 V, the ESD protection circuit diodes will turn on and clip the signal, reducing linearity.
What is needed is an ESD protection system that provides extra headroom at the I/O pad in relatively low supply voltage ICs.